OB-6 CV generation revisited

After getting the closeups of the OB-6 it's time to put together what I've learned so far.

Hardware

1) The DAC used is AD5668, an 8 channel 16bit DAC with built in voltage reference (2.5 x 2 = 5V). The chip used by Sequential is the AD5668-3 that resets to midscale (2.5V). 

2) The multiplexers are TI CD74HCT4051

3) The op amp buffers are most likely TL06x as that's about the only thing found on the voice card

4) There is no DAC output buffering op amp as that is built into the DAC.

5) I'm not sure what size of sample and hold caps they are using

Timing/performance

Brian from Abstrakt Instruments has a great breakdown of how the refresh is done here:

https://youtu.be/4WwXlRYw_S0?t=1937

Each DAC channel updates 8 cv channels at 24kHz meaning

• DAC channels are updated at 192kHz
• There is about 5.2uS available for refreshing a single CV, this includes time to set the DAC, cap charging and any propagation delays/slew through the mux.
• From the oscilloscope output, a full rail to rail change takes around 3uS

DAC performance

• The DAC has a max SPI speed of 50MHz, meaning one bit takes 20nS to transfer. Each update is 32bits long, meaning updating 8 channels takes at least 32 * 8 * 20nS = 5120nS = 5.12uS.
• Settling time is typically 2.5uS, but can be as bad as 7uS. (But it is stated that this is 1/4 to 3/4 settling so that means that it is only a change of 2.5V?)
• Slew rate is 1.2V/uS

Multiplexer performance

• On resistance is 90-180Ohm (?)
• Propagation delay from in to out is 4nS, higher with higher capacitive load but still in the nS range
• Switch delay is around 20nS
• Charge injection: does not say.

What does this mean in practice: 

Well, we've got 5.2uS to update a single CV. First of all, if updating all channel takes 5.1uS, this cannot be done during that period. We want to update all channels at once, if we didn't we would need separate address lines for all the multiplexers which is infeasible. 

Luckily the DAC has a LDAC pin. This means we can write data to all channels, and when ready, flip the LDAC and load channels at the same time. By writing the next update while the current one charges the capacitors, we have just enough time to do a full 8ch update. We will also have to use hardware "fire and forget" SPI, writing the necessary 32 bytes of data in the background. If we use blocking SPI, we will have no time left between updates to calculate the next bytes!

Next, we still have to let the dac settle before we turn on the multiplexer output, or we would see an error in the voltage. Settle time is, from both the oscilloscope photo and the datasheet, around 3uS, but it could be as bad as 7uS. I would also think that the slew rate of 1.2V/uS also means that it would take around 6uS for a 5V change.

The multiplexer propagation delay is negligible. That leaves 2uS for charging the cap and turning off the mux again. 

Now, as I've noted in earlier posts, I could charge a 10nF cap rail to rail at 40kHz from a TL072, meaning charge times are around 25uS.  2uS means we need to use a cap at least 1/10th that size, or less than 1nF. 

I did some tests with the DAC8830 and a DG408 multiplexer. Using a 1nF cap did NOT let us fully charge the cap rail to rail in the 5.2uS window.  I got close but not close enough. The AD5668 may be able to deliver more current but that remains to be tested. 

So what do I make of all this? 

I suspect that Sequential is "cheating" here. They haven't spec'ed their system for charging rail to rail in <5uS, as they don't have to! The fastest moving signals would be the envelope attacks, and those NEED intermediate steps to sound good (?). 

I have ordered both the AD5668, CD74HCT4051 and TL072. It will be exciting to see the results of using those parts. Will I still have the charge injection issues? Does the AD5668 charge the caps faster? I will definitely post the results!