DCO: Switching to JFET to try to improve low frequency amplitude

To try to fix the issue I'm having where the saw wave amplitude is too low at low frequencies, I decided to redesign the core using a JFET in place of the BJT that resets the integrator.

I found no p-channel JFET in my parts box, but I had plenty of the J112 n-channel JFETs, so to make things easier I decided to go with the yusynth design.

The Yusynth design however, has a 0-5V saw wave, whereas mine is 0 to -10V. To make sure things would still work, I changed the core ever so slightly to get a 0-10V:

instead of tapping the charge voltage directly from the DAC using a positive opamp buffer, I switched to a unity gain negative amplifier. This would sink current instead of sourcing it, changing the charging direction. To make this works one also have to replace the 2n3906 PNP transistor with a 2n3904 NPN (One should also switch the polarity of the timer output, but as both a positive and negative going spike are generated, just slightly offset in time, this was not required for testing).

But testing this, I got a big surprise - the low frequency amplitude was no longer too low - it was too high! Previously I had to increase the DAC value from 60 to 80-something, now I had to reduce it from 60 to 48 (steps times 5V/65536).

This made me less certain that switching to a JFET would improve anything, but I still decided to try it.

I added an LM311 comparator, and set its negative input to 0.118V using a 120k and a 4k7 resistor. This would assure that when the positive input was just slightly higher than 0V, the output would spike up to 15V, and when the input was 0V the output would be -15V - similarly to the yusynth circuit, where the comparator outputs a negative voltage to turn off the JFET. The circuit worked instantly (!), but as suspected, nothing changed.

So, now I guess I've ruled out the reset transistor as the cause of the offset. Also, the fact that the amplitude error changes when I swap the charging polarity, makes me believe that the cap is not at fault either (though I will still check this).

That leaves either the DAC (which is unlikely for the same reason as the CAP) or the opamp buffer.

It could also be that a small difference in the power lines (measured to +15.01 and -15.00 volts) could cause this, I don't know. I will try recalibrating and also try different opamps to see if that changes anything.

For reference: Here is the original breadboarded circuit with the 0 to -10V output. I have since added the missing 2R2 resistor, however, that changed nothing. The DAC is connected where the 20k pot is in this drawing

Yusynth VCO core discharging

I may have written about this before, but here goes:

The Yusynth saw core ramps down from 5 to 0v, then resets to 5v. the top of the charging cap is always at 5V while the bottom drops towards zero as current is sunk through the expo converter (u4).

The LM311 comparator has its positive leg grounded (when sync is not used). The LM311 is an open collector type comparator. For these, the rule, as written here, is that: 

"Current WILL flow through the open collector when the voltage at the MINUS input is higher than the voltage at the PLUS input.

Current WILL NOT flow through the open collector when the voltage at the MINUS input is lower than the voltage at the PLUS input."

When current does NOT flow, the output is pulled towards 15V via R20. When current flows, the output is pulled towards -15V which is connected to pin 1 of U5.

Pin 1 is called ground, but it can be connected to a lower voltage if necessary.

During capacitor charging, the voltage at the minus input is positive and thus higher than the positive input. In this case, current flows and the output is negative.

Once the negative input reaches 0V, for an instant, the input is lower than the voltage at the positive input, and current stops flowing. The output is then pulled towards +15V.

This would mean that as long as the output is negative, the JFET transistor is switched off, and once the output is positive, the JFET conducts, resetting the cap.

This is in accordance with what wikipedia says about an n-channel JFET:  "To switch off an n-channel device requires a negative gate-source"

 The source and drain of the transistor will always be between 0V and 5V, thus a -15V gate voltage assures that it is turned off. Similarly, source and drain will never be above 5V, so a +15V will always turn it off.

Since the source/drain may however reach 0V, the emitter of the transistor cannot be connected to ground - this would leave the comparator output and thus the JFET gate at about 0.6V, which is not enough to keep it pinched off.