Power and DAC

It's been a busy week. I've designed prototype cards for an AD5557 based DAC card (parallel input dual output) and a separate multiplexed 2-input 32-output sample and hold card, and sent both off to OSHPark for production.

Today I designed two PSU cards based on Ken Stone's CSG66 module - one dual voltage (+/- 15V) and one single voltage (2.2-9.6V) that I'll use as the analog and digital PSU in future projects.

Sample and hold hold time

I am trying to figure out if the simple s&h circuit can hold its charge at a usable level long enough to update 32 units with only one dac.

Returning to the prophet 5 service manual, they indicate that their cycle time is 8ms, that they update 41 channels and that each channel update takes 20us for the DAC to settle and then 30-40us for the s&h to setle as well.

I made a little POC cirucit that held a mux output high for 25us then switched it off for 1ms. I could not see any drooping on the s&h (surprisingly it droops upwards towards 15V when nothing is connected to the input), but this is of course no proof as I am aiming for a very high output resolution - the Prophet 5 has a 7 bit dac whereas I will use a 14 bit one. Still, I will hopefully be able to update all 32 channels in around 0.8ms, which is 1/10th of the time it takes for the prophet 5, so it might not be impossible after all.

Top line is s&h output. Some noise is visible while the s&h is acquiring its value (when the bottom line is low), this may just be because I used an opamp 2.5V output as "DAC out".

I will try building a dual 16 channel s&h and see how that works out.

Sample and hold acquisition time

I did a quick test on a home made sample and hold circuit to figure out how fast it settles (reaches a stable state).

The circuit consists of a 10nF capacitor and an opamp buffer, similar to what you will find in the Prophet 5 and the Jupiter 8.

The prophet 5 service manual says that they let the sample and hold settle for 30 to 40 uS. I connected the circuit to a function generator's square wave output and the output to a oscilloscope. Finding the maximum frequency was then only a matter of observing when the output no longer reached its peak within the time before the square wave changed polarity.

With a 10V p-p input, the s&h managed about 10kHz on the function generator. Since the s&h changes on both high and low parts of the wave, the s&h frequency is in fact 20kHz, meaning that the acquisition time is 50uS.

When changing the input to 5V p-p I was able, unsurprisingly, to reach 20kHz on the function generator, which means an acquisition time of 25uS.

Vertical resolution: 2V/square, Horizontal resolution: 20uS/square. Squares are input, slanted ones are output.

I am aiming for a 32 channel controller, which means that with a 40kHz S&H I get a maximum refresh rate per channel of 1250Hz. It remains to be seen if this is fast enough for pitch bends etc.

Old school din-based midi runs at 31.25 kbits/s. Each 14 bit pitch bend takes up 16 bits, which means that the maximum midi pitch bend rate is 1953Hz. Perhaps 1250Hz is enough, if not, I have to use a dual channel dac with two 16channel s&h, and update two and two at the same time.

Working OMM prototype

I've spent the days since getting back to Norway making an OMM prototype running on an 8 bit PIC18F458 @ 20MHz.

Things are looking very good indeed, except for speed of course. I've implemented:

- node structs
- function pointers and pointer lookup
- matrix array calculation
- DAC output to 14 bit SPI DAC (MAX544
- input buffer reading and outputbuffer writing

In addition I've coded the following node functions:
- Sum
- Invert
- Invert each side (positive stays positive etc)
- Ramp (but without proper interval calculation)
- Delay line (allows loops in network)
- Input
- Output

Next up should be
- Timers for constant output to DAC
- SPI input for controllers (but that is not possible without a second SPI module)
- JSON parsing
- Table lookup for tuning and exponentialization.

Here is the first output from the OMM - the frequency is too low to get a good image on the scope:

A few specifics on the SPI and the DAC:

The DAC accepts a maximum SPI speed of 10MHz. In the tests I did, I ran the SPI at F_osc/4, which means 5MHz when the oscillator frequency is 20MHz. I achieved what I think is a sample rate of about 89kHz but that is without any calculations between samples. In practice then, it seems the maximum DAC rate is slightly less than 180kHz when running the SPI clock at 10MHz (from the PIC that is, it is entirely possible that you can achieve higher speeds otherwise).

Here is  the code for the DAC tryout:

void writeToDac(){
	unsigned int dacout;
	/**** DAC ****/
	SPI1_Init();
	TRISC = 0; //trisc as output
	LATC.B0 = 1;
	dacout=0;
	// The following code runs at about 89kHz.
	while(1){
	LATC.B0 = 0; //must write directly to latch (didn't work with PORTC.B0!)
	SPI1_write(hi(dacout));
	SPI1_write(lo(dacout) & 0b11111100);
	LATC.B0 = 1; //latches values in DAC.
	dacout += 2048;
	}
	}

The first time I got the DAC working it looked like this:

The visible steps are because I chose to use only 32 steps to speed things up and to see what is happening. After removing all delays and maximizing the speed it looks like this:

Here is the SPI clock btw: