VCO testing again

I need to test the range of the CEM3340 based VCO with various pots at their min/max and also replaced with resistors or just leftout.

The pots in question is

- Osc scale trimmer, located on the board

- HF tracking trimmer, external. The Prophet 5 does not use this

- The 500k CV input offset trimmer. The reference design uses a 360k here, the P5 uses a 357k.

 

Now, for some reason there is a lot of noise on the board outputs (the CEM itself is clean), but even so I am able to measure the frequencies.

 

For all tests, unless specified, I'm running with

360k resistor instead of 500k pot

HF trim center (5k/5k)

27k CV input, meaning the CV should span 18.5 octaves if perfectly tuned (and if that's supported by the VCO, which it isn't).

A cold VCO, i.e. turned on briefly to measure but otherwise off. 

PS: My resistors are to 12V, not 15V. Also, I have a 1M5 hardwired to -12V so basically the same as the Prophet 5 (though that uses -15V)

Test 1

Osc scale trimmer (10k) fully counter clockwise

Max period: 264ms (0V): 3.79Hz

Min period: 28.4uS (2.8V): 35.2kHz

Test 2

Osc scale trimmer aprox center (so around 29k to -5 from pin 1)

Max period: 492ms (0V): 2.03Hz

Min period: 28.2uS (3.6V): 35.36kHz

Test 3

Osc scale trimmer fully clockwise: (10k top, 0k bottom, so 24k from pin1 to -5V)

Max period: 650ms (0V): 1.54Hz

Min period: 28.4uS (4.5V): 35.2kHz

Test 4

Osc scale trimmer fully counter clockwise

HF trim trimmer fully counter clockwise (0k left to summer, 10k right to HF tracking)

264ms / 3.79Hz

28.4uS at  2.78V CV

Test 5

Osc scale trimmer fully counter clockwise

HF trim trimmer fully clockwise (10k left to summer, 0k right to HF tracking)

265mS / 3.79Hz

28.7uS at 2.6V: 34.8kHz

Test 6

Osc scale trimmer fully clockwise

HF trim trimmer fully counter clockwise (10k left to summer, 0k right to HF tracking)

649mS / 1.54Hz

30uS at 4.8V: 33.3kHz

Test 7

Osc scale trimmer fully clockwise

HF trim trimmer fully clockwise (10k left to summer, 0k right to HF tracking)

656mS / 1.54Hz

31.1uS at 4.1V, not possible to get lower: 32.2kHz

Test 8

Osc scale trimmer approx center

HF input directly to GND

457mS / 2.19Hz

 28.7uS at 3.8V, 28.4uS at 5V: 34.8kHz

Test 9

Osc scale trimmer fully clockwise

HF input directly to GND

VCO has been on for a bit

4V gives 20.8kHz 

Then

51.8uS = 19.3kHz (not sure if I changed the CV so not very informative)

29.8uS is max = 33.5kHz

 

Test 10+

After staying on for at least 30min

656mS / 1.52Hz

29.2uS max

4V gives 52.27uS so 19.1kHz

Little change from intitial, cold masurements, still tunable over full range.

Then fully counter clockwise osc scale trimmer: 

263mS, exact same as with cold VCO.

 

Conclusion

I may just go without HF tracking (connect to GND) and shorting bottom two pins of Osc scale pot - or use a 10k for higher precision tuning at the sacrifice of lowest possible note. All options seem to allow for plenty of digital tuning.

Sync

Connecting a function generator to the VCO sync inputs, I got the following:

Hard sync is only triggered on fast falling edges. This means that the input must either be a pulse or a rising saw. Double check what the DCO outputs!

Sync is triggered on the falling edge of the input square wave

 

CEM Hard sync

expected input (bottom) and effect on saw wave (top)

CEM Hard sync is currently not working very well, but I found this post http://atosynth.blogspot.com/search/label/VCO saying I had the same problem earlier and that adding a 1nF cap in series with the input may fix things. Anyway, my experience is this:

For positive going sync pulses (with PWM making the positive going part 10%), the "neutral"/ 0V part must be less than -0.66V (which is eerily similar to one diode drop). 

Top is triangle output, the small dips are the classic CEM hard sync effect of positive going pulses. Zero must be around -0.7V

 

If I drop the lower level to less than -1.63V it stops working again. But - if I reverse the pulse so the 10% part is the one dropping, and set the MAX value to <-0.66V, it starts working as it should again.

Negative going pulses, zero must still be about -0.7V negative for things to work

Ring modulator LTSpice simulation

Before breadboarding the circuit again I thought it would be a good idea to simulate it to see what effects to expect when replacing pots and caps.

The circuit as found on the Yusynth pages (http://yusynth.net/Modular/EN/RINGMOD/index.html)

The LM1496-model was found here: 

https://forum.allaboutcircuits.com/threads/mc1496-monolithic-balanced-modulator-spice-model.47212/

With the pots centered, two 10Vpp input waves result in a 8Vpp output.

Signal and carrier

Green is output

With the 220Ohm pot fully turned to one of the sides, we get this:

 

With the 500Ohm pot fully turned to one of the sides, we get this:

It looks like the wave with the longest wavelength has gotten a DC offset

Now, if we replace the 220Ohm pot with a 500 one we get the exact same waveform when centered, byt at one of the sides we get this:

If we reduce the wiper to half way between center and one of the sides we get back to what we saw with 220Ohm:

It is thus likely that the 220Ohm potentiometer may be replaced with a 500Ohm one.

Cap biasing

The 1uF input cap on the left looks like it has one side DC biased between -3V and -4V:

The 1uF input cap on the right looks like it has one side DC biased around +7.5V

As for the 100uF cap, it is biased at around 6.5V. I cannot see any changes to the output whether I use a 200uF, 100uF, 10uF or no cap here, not with a combination of 1MHz and 10kHz, nor with the combination 1kHz and 10Hz. I think I will try using a 100uF ceramic even with the capacitance dropped to much lower by the DC bias issues such caps have.

Now, these are just simulations of course, so things may be different in practice, but it looks promising - I may be able to standardise on 500Ohm pots and use ceramics instead of electrolytics for the other caps. 

UPDATE: I have even used 500Ohm pots on my prototype so I will be fine :-D

EDIT: Input and output DC blocking / offset caps

I simulated the frequency response for the input. A 1uF cap gives a 3dB point at around 1Hz.

 

As the cap is DC biased at 7.5V, its capacitance may in practice be as low as 0.1 to 0.2uF. It would then have a 3dB point around 10Hz.

If we use a 10uF cap instead, this would in the worst case have a capacitance around 1-2uF, matching the specified 1uF. If id is NOT reduced, a 10uF cap should have a 3dB point even lower than 1Hz and we should still be fine - I hope!

Ceramic capacitors and DC biasing

I am considering replacing many of the high value capacitors in my circuits, which are usually electrolytic caps, with ceramics.

There is however an issue -  ceramic caps have a strange property: if they are DC biased, e.g. normally have a certain voltage across them, the effective capacitance changes:

https://community.infineon.com/t5/Knowledge-Base-Articles/DC-Bias-characteristic-of-Multilayer-Ceramic-Capacitor-MLCC/ta-p/250035

The capacitance change is relative to the capacitor size, so 1206 caps do not change as much as 0603 for example. The voltage rating however, has little effect.

As an example, if one side of the cap is connected to ground, and the other has a signal that swings around 4V, the effective capacitance will be just 30% of the rated value if we're using an 0603 cap. Using a 1206 instead gives around 70%.

C0G caps are not as affected by this as X7R, X5R, but in return they are bigger and not readily available in as high capacitances.

https://www.kyocera-avx.com/docs/techinfo/CeramicCapacitors/mlcc-dc-bias-characteristics.pdf