Saturday, May 11, 2024

Clip detection

I want to detect when the signal on the mix bus is about to clip, to be able to indicate it in the UI.

I initially intended to use the Elliot Sound Products clip detection circuit to do bipolar detection:

There are a few issues with this though. First of all, the output after the diodes is 0-10V, which is too high to be used directly with the mcu inputs.

 Second, as I will not interface this directly with the mcu, but rather with the PCA9539 port expander, it won't trigger an interrupt. Instead, I have to poll the signal - so I need to latch the state whenever a clipping pulse is received, and reset state after I've read it.

It is possible to make an SR-latch using an op amp, as described here https://www.radiolocman.com/shem/schematics.html?di=463517 and here https://www.edn.com/use-an-op-amp-as-a-set-reset-flip-flop/


 After a bit of fiddling with my simulation, I was able to come up with this circuit:

The output of the comparator op amps is +/- 10.4 approx. This is dropped to around 0-9.8 through the diodes. R3 and R4 divides the signal down to around 3.3V. It is then buffered, and inserted into the latch through the diode (dropping an additional 0.6V). R15 and R16 sets the value seen at the negative pole of the last op amp when in2 (reset signal) is turned off. R14 adjusts the reset voltage so we're able to reset the latch, and D3, R17 and R18 reduces the output from +/-10.4V to 0-3v3, ready for the MCU.

After even more fiddling, trying to reduce the number of components, I ended up with this:


It works just as well as the previous one.

Green: input at positive terminal of the right op amp. Blue: Reset signal. Red: latch output

 

Now, I did a lot of testing with this circuit and it has one big issue. At frequencies of around 5kHz (with a triangle input) the comparators are too slow, so the peaks are not high or long enough to properly set the latch. As we get closer to 20kHz it simply stops working. If I lower the detection voltage (replace the 1k resistors with 2k2 for example), it works, but the clipping voltage level changes with frequency. That's not very good - though it may be GOOD ENOUGH.


Enter V2.

Let's do this the proper way.

By replacing the op amps with LM311 comparators, and the op amp-based latch with a real latch, CD4043, things work fine all the way up to 20kHz+:

The 10pF caps are not necessary, and the 10k/100k/10k voltage divider at the input can be replaced with 1k/10k/1k.

The CD4043 is driven from a 3v3/GND PSU, so level shifting is not necessary.

 

An imporant thing to note here is that the top comparator has the collector (pin 7) connected to 3v3 and the emitter (pin 1) connected to GND through a 10k resistor. In this configuration, the output (connected to pin 1) will be high whenever the voltage at the negative input (3) - our signal - is higher than the voltage we compare against (2, 10V), and the voltage range is 0 to 2.7 approx. CMOS inputs are considered ON when the voltage is > 2V (for 3v3 supplies) so this is fine.

For the bottom comparator, the collector is connected to 3v3 through a 10k resistor and the emitter is grounded. The output (connected to pin 7 this time) is positive whenever the voltage at the negative input (3) - our signal - is lower than the voltage we compare against (2, -10V).

As the signals are fed into different latches (there are four available in one CD4043), we actually have separate clipping indicators that we could read if we wanted to. This is not necessary for my use, so I simply combine them using two diodes (again, dropping the voltage, but it still works with the PCA9539).

Positive clipping only

Negative clipping only

 

 

 

Some action shots

White = reset signal
Brown = clipping state, as seen by microcontroller
Orange = output from CD4043 comparator (v2)
Red = output from LM311 comparator for high clipping
Blue = output from op amp latch (v1)
Yellow = input signal from function generator

4.8Hz input, says 19.5Vpp on function generator (fg) but is about 20Vpp measured. Both versions trigger

48Hz, 19.4Vpp on fg. Both versions trigger

517Hz, 19.4Vpp on fg. Only v2 triggers.

517Hz, 19.5Vpp on fg. Both versions trigger again.

5kHz, 19.4Vpp on fg. Vmax is > 10V so both should trigger. Only v2 triggers

5kHz. We have to go all the way to 20.1Vpp on the fg to get v1 to trigger


10kHz, have to increase to 20.5Vpp on fg to get v1 to trigger

20kHz, v1 doesn't trigger even at 20.9Vpp on fg


Wednesday, April 24, 2024

VCO testing again

I need to test the range of the CEM3340 based VCO with various pots at their min/max and also replaced with resistors or just leftout.

The pots in question is

- Osc scale trimmer, located on the board

- HF tracking trimmer, external. The Prophet 5 does not use this

- The 500k CV input offset trimmer. The reference design uses a 360k here, the P5 uses a 357k.

 

Now, for some reason there is a lot of noise on the board outputs (the CEM itself is clean), but even so I am able to measure the frequencies.

Update: The noise is still there when switching to a different VCO PCB.

 

For all tests, unless specified, I'm running with

360k resistor instead of 500k pot

HF trim center (5k/5k)

27k CV input, meaning the CV should span 18.5 octaves if perfectly tuned (and if that's supported by the VCO, which it isn't).

A cold VCO, i.e. turned on briefly to measure but otherwise off. 

PS: My resistors are to 12V, not 15V. Also, I have a 1M5 hardwired to -12V so basically the same as the Prophet 5 (though that uses -15V)


Test 1

Osc scale trimmer (10k) fully counter clockwise

Max period: 264ms (0V): 3.79Hz

Min period: 28.4uS (2.8V): 35.2kHz

Test 2

Osc scale trimmer aprox center (so around 29k to -5 from pin 1)

Max period: 492ms (0V): 2.03Hz

Min period: 28.2uS (3.6V): 35.36kHz

Test 3

Osc scale trimmer fully clockwise: (10k top, 0k bottom, so 24k from pin1 to -5V)

Max period: 650ms (0V): 1.54Hz

Min period: 28.4uS (4.5V): 35.2kHz

Test 4

Osc scale trimmer fully counter clockwise

HF trim trimmer fully counter clockwise (0k left to summer, 10k right to HF tracking)

264ms / 3.79Hz

28.4uS at  2.78V CV

Test 5

Osc scale trimmer fully counter clockwise

HF trim trimmer fully clockwise (10k left to summer, 0k right to HF tracking)

265mS / 3.79Hz

28.7uS at 2.6V: 34.8kHz

Test 6

Osc scale trimmer fully clockwise

HF trim trimmer fully counter clockwise (10k left to summer, 0k right to HF tracking)

649mS / 1.54Hz

30uS at 4.8V: 33.3kHz

Test 7

Osc scale trimmer fully clockwise

HF trim trimmer fully clockwise (10k left to summer, 0k right to HF tracking)

656mS / 1.54Hz

31.1uS at 4.1V, not possible to get lower: 32.2kHz

Test 8

Osc scale trimmer approx center

HF input directly to GND

457mS / 2.19Hz

 28.7uS at 3.8V, 28.4uS at 5V: 34.8kHz

Test 9

Osc scale trimmer fully clockwise

HF input directly to GND

VCO has been on for a bit

4V gives 20.8kHz 

Then

51.8uS = 19.3kHz (not sure if I changed the CV so not very informative)

29.8uS is max = 33.5kHz

 

Test 10+

After staying on for at least 30min

656mS / 1.52Hz

29.2uS max

4V gives 52.27uS so 19.1kHz

Little change from intitial, cold masurements, still tunable over full range.

Then fully counter clockwise osc scale trimmer: 

263mS, exact same as with cold VCO.

 

Conclusion

I may just go without HF tracking (connect to GND) and shorting bottom two pins of Osc scale pot - or use a 10k for higher precision tuning at the sacrifice of lowest possible note. All options seem to allow for plenty of digital tuning.

 

Update: Resistor instead of Osc scale trimmer

I did some measurements over the full range of the oscillator, first with the trimmer at its maximums, then with three different resistor values. For each, I calculated an "expected frequency", setting the measured frequency closest to 440Hz as 0, then I calculated an error as 100*(expected - measured freq) / expected.

Error with pot at extremes (blue and red) and then with a 3.9k resistor (breakdowns are when we reach the max VCO frequency of approx 35kHz)

Error using three different resistors

 

The best result was reached using a 2.7k resistor for a total of 26.7k between input and -5V. As the graph shows, we are within around 5% of the correct value and it fluctuates around 0, so I don't think we can get any closer. All measurements are done by manually setting the CV and measuring ms as the distance between two tops in Logic2, so there is a significant source of error there as well.

What I DONT know is if this is if this is consistent between VCO chips and VCO PCBs, so perhaps its best to keep the pot. If I decide to redo the PCB though, I think I'll go with a fixed resistor here.

Update: Double capacitance

I had forgotten that the VCO PCB comes with an on-board cap, so the external cap is not necessary. This means that all measurements above are for a 2nF cap instead of a 1nF, meaning the frequencies measured are half of what they will be with a 1nF cap (but not sure what the max frequency will be)

With a new AS3340 and only one 1nF cap, the lowest frequency is 185.3ms = 5.4Hz. Max is 15.2uS = 65.79kHz. The tracking with a 2k7 resistor is similar to the 2nF version and also similar to that of the other AS3340 which is good. There is a difference of around 3% (2Hz vs 2.7Hz) for the lowest frequency between the two devices though.

The tracking is similar, 1uF may even be a tad better - but the frequency range is different (2Hz to 32kHz with 2uF, 5.4Hz to 66kHz with 1nF)

Range

Both VCOs top out at 3.25V CV.

With a 2nF cap the range is 2 to 32kHz. The bottom is 2-3 octaves lower than necessary unless the VCO is used as an LFO.

With a 1nF cap the range is instead 5.4Hz to 65kHz which is at least one octave more than necessary on the top of the range.

The higher the range of frequencies covered by the CV, the less accurate the CV will be. Noise will also affect the CV more. Thus, we should try to keep the CV within the usefull range while still allowing room for trimming.

Since the lower range is at 0V CV, we'd have to mix in an offset to rise it. As for the top, we can replace the 25k input (which gives a theoretical range of 20 octaves) with a smaller one.

Let's say we want a useable range from 20Hz to 20kHz. And then we would like an additional octave at top and bottom for tuning. Thats 10 usable octaves plus 2 for tuning. 

With a 100k 1V/oct summing point we get 10uA per octave. 12 octaves needs 120uA, and to get this from a 5V we need a 5V / 120uA = 41.67kOhm resistor. Using a 39k resistor gives us 128uA (or 12.8 octaves). 33k gives 151uA (or 15.1 octaves).

Either of these may be fine, it all depends on how much the VCO drifts.

A quick test with a 39k resistor gives a range of 5.4Hz to 38Hz as expected. 

Adding a 470k resistor between a 5V reference and the CV summing point rises the bottom to 11.5Hz and puts the top at 66kHz. I think this is a good compromise.

Update: My reference voltage is 2.5V, not 5V, so using a 270k resistor instead is better.

Sync

Connecting a function generator to the VCO sync inputs, I got the following:

Hard sync is only triggered on fast falling edges. This means that the input must either be a pulse or a rising saw. Double check what the DCO outputs!

Sync is triggered on the falling edge of the input square wave

 

CEM Hard sync

expected input (bottom) and effect on saw wave (top)

CEM Hard sync is currently not working very well, but I found this post http://atosynth.blogspot.com/search/label/VCO saying I had the same problem earlier and that adding a 1nF cap in series with the input may fix things. Anyway, my experience is this:

For positive going sync pulses (with PWM making the positive going part 10%), the "neutral"/ 0V part must be less than -0.66V (which is eerily similar to one diode drop). 

Top is triangle output, the small dips are the classic CEM hard sync effect of positive going pulses. Zero must be around -0.7V
 

If I drop the lower level to less than -1.63V it stops working again. But - if I reverse the pulse so the 10% part is the one dropping, and set the MAX value to <-0.66V, it starts working as it should again.

Negative going pulses, zero must still be about -0.7V negative for things to work

Adding a 1nF input cap to the cem hardsync input

That fixed everything, now it looks like this, given a square wave input




Frequency modulation

Exponential FM through a 100k resistor works as expected, giving a +/-5 octave FM if VCO is trimmed properly.

Exponential FM

 

Linear FM did not work out of the box. If input is < -1V through a 120k resistor the output flatlines, I had this in my design and it does not work. So what DOES work?

Linear FM, VCO flatlines when FM input is too low

 

About linear FM in the CEM3340 manual: 

The input resistor should be selected to produce a current equal to +/- the reference current when the max input signal is present. 

The reference current is set using R_r. In the datasheet, the reference current is 15V / 1M5, or 10uA. Since I'm still using a 1M5 resistor but elected to use a 12V supply instead, I have ended up with a 12V/1M5 = 8uA reference current.

R_r is the reference-setting resistor

 

In the original circuit, the linear FM input resistor is set to 1M. To get a +/-10uV input here would mean the input would have to be +/-10V.

For my oscillator, the linear FM input will be max +/-5V, and I need to match a 8uA current. U/I, or 5V / 8uA = 625kOhm, which means I should use a 470k and a 150k resistor in series.

Linear FM with a 620k input resistor works fine.

 

One more thing - I want to be able to do linear modulation with CV. I therefore have to sum the input before 620kOhm input. Also, the CV is 0 to 5V when it should really be -5 to 5V. Thus, I should set CV gain to 2 and subtract 5V to center it. But the 100nF cap at the lin FM will filter out any DC component, so centering does not do anything. Instead, the CV from the CV generator should stay at 2.5V when not in use. It must also be amplified to 0-10V. That way it stays at 5V when 'idle' and can drop by 5V when in use.

PS: Slow moving lin FM will not be possible.
PPS: Centering the CV won't do any harm, it just won't do any good either, except keeping the lin FM input a bit further away from the rails when summing with another input.

Also - If I use a normal inverting summer, the CV will be reversed. This can be fixed digitally. The analog input will also be inverted, but I don't think that's an issue.

Noise issue

The noise is present on the frequency CV as well as on the output



The CEM saw output is completely clean, so the noise is introduced later

The same noise is present on the -5V reference voltage, with an total offset of around 25mV.

The noise on the -5V line is not affected by the oscillator frequency

The noise on the 

Changing the reference op amp did not change anything

Connecting the scope to the output through a 1k resistor has no effect.

The noise is 80kHz

Buffering the output does not change anything.

The noise is present on the CV even when not connected.

The noise is not present on the 5V reference, but it is present on the -5V/Vee input. Replacing the inverting op amp does not change anything:


When removing the VCO PCB from the breadboard, the -5V stabilizes and the noise disappears from the CV:


Something weird is going on. While tweaking the frequency CV, for a brief moment, the noise disappeared. This happened a couple of times. At the same time, the CV has stopped working after I put the PCB in the wrong position on the breadboard. Very strange.

Oh, but now something happened. Instead of tapping -5V directly from the inverting op amp, I buffered the voltage in a second op amp. Now the noise is gone! (Offset is still wrong though. Perhaps the CEM wave outputs are too low when not running from 15V?).


CV input seems dead though. I need to try a different AS3340 chip but I can't find them...

Noooo! The noise is back! But unplugging and plugging back the -5V made it go away again. Something is ringing.

But when moving the probe from triangle to saw output, noise came back. 

Ooh, touching the summing point of the 5 to -5V inverter op amp makes the noise come back (touching the other side of the feedback resistor doesn't.

I think that, in any case, I should reconsider using an op amp for the negative supply here!!! I'm actually embarrassed I ever did.

Wave amplitude and centering

The output from the CEM is 0 to 8V for saw and 0 to 4V for triangle:


The datasheet says 0-10V for saw and 0 to 5V for triangle. In other words, using +12V instead of +15V has reduced the amplitude by 20%, which screws up my centering and amplification. D'oh.

The output from the pcb is -3 to 5V for saw and triangle, -4.4 to 4.8V for square. Unfortunately, since we're using the 0-crossing of the triangle for pulse width generation, the pulse width is also wrong.


Fixing it:

- Ok with positive summer but must have high input impedance. Same when using saw for pwm


Running the CEM3340 from +/-12V instead of +12/-5V

The CEM3340 datasheet uses a 820Ohm resistor from pin 3 to -15V. This works with my version as well (and the hard sync transistor may be connected to -12V instead of -5V without any issues).

However, I had a hard time getting the oscillator to track - I increased the 2k7 resistor on input 1 all the way to 22k (=22k+24k total), and while this made things better, I just couldn't get back to the 1V/oct expected. To stop wasting time I've decided to go back and use a 79L05 to generate -5V on the PCB itself.

However - this gave an unexpected error. Without a 100nF cap on the 79L05 output, the CEM just would not start oscillating!

With -5V from an inverting op amp, it works:

Red is saw out, orange is -5V from op amp

 

With a 79L05 without a cap on the output, the CEM3340 just doesn't start oscillating:

Red is saw out, orange is -5V directly from 79L05 (without a 100nF cap to gnd)

Adding the cap makes the CEM3340 start as it should

Red is saw out, orange is -5V directly from 79L05 (WITH a 100nF cap to gnd)

Final values

After a lot of measuring I've ended up with the following values:

- 5V negative PSU (79L05)

- 39k CV input resistor 

- 2.7k + 24k tracking resistors (Though a pot may still be a good thing)

- 270k to 12V pitch offset resistor


With these params I'm able to get 12Hz to 20kHz, 20kHz is at a little more than 4V CV so still room for tuning.

I tested two different AS3340s, and they differ slightly in both tracking and base note (CV=0) so it may still be necessary to use a trimmer in place of the 2k7. 

Tracking is pretty similar

Frequency is fairly even too

Actual values


Tracking with a 25k CV input resistor, 0.25V gives almost exactly 2 x frequency, meaning 1V/octave at 100k is pretty accurate.

Friday, April 19, 2024

Ring modulator LTSpice simulation

Before breadboarding the circuit again I thought it would be a good idea to simulate it to see what effects to expect when replacing pots and caps.

The circuit as found on the Yusynth pages (http://yusynth.net/Modular/EN/RINGMOD/index.html)

The LM1496-model was found here: 

https://forum.allaboutcircuits.com/threads/mc1496-monolithic-balanced-modulator-spice-model.47212/


With the pots centered, two 10Vpp input waves result in a 8Vpp output.

Signal and carrier

Green is output

With the 220Ohm pot fully turned to one of the sides, we get this:

 

With the 500Ohm pot fully turned to one of the sides, we get this:

It looks like the wave with the longest wavelength has gotten a DC offset

Now, if we replace the 220Ohm pot with a 500 one we get the exact same waveform when centered, byt at one of the sides we get this:

If we reduce the wiper to half way between center and one of the sides we get back to what we saw with 220Ohm:

It is thus likely that the 220Ohm potentiometer may be replaced with a 500Ohm one.

Cap biasing

The 1uF input cap on the left looks like it has one side DC biased between -3V and -4V:

The 1uF input cap on the right looks like it has one side DC biased around +7.5V

As for the 100uF cap, it is biased at around 6.5V. I cannot see any changes to the output whether I use a 200uF, 100uF, 10uF or no cap here, not with a combination of 1MHz and 10kHz, nor with the combination 1kHz and 10Hz. I think I will try using a 100uF ceramic even with the capacitance dropped to much lower by the DC bias issues such caps have.


Now, these are just simulations of course, so things may be different in practice, but it looks promising - I may be able to standardise on 500Ohm pots and use ceramics instead of electrolytics for the other caps. 

UPDATE: I have even used 500Ohm pots on my prototype so I will be fine :-D

EDIT: Input and output DC blocking / offset caps

I simulated the frequency response for the input. A 1uF cap gives a 3dB point at around 1Hz.

 

As the cap is DC biased at 7.5V, its capacitance may in practice be as low as 0.1 to 0.2uF. It would then have a 3dB point around 10Hz.

If we use a 10uF cap instead, this would in the worst case have a capacitance around 1-2uF, matching the specified 1uF. If id is NOT reduced, a 10uF cap should have a 3dB point even lower than 1Hz and we should still be fine - I hope!