DAC8565 and 16ch sample and hold

I intend to use the DAC8565 quad 16 bit DAC for the XM8, I've even bought 20 of them on breakout board and written a test - but for some reason, I haven't written anything about it.

Right now I'm making the final CV mux board, so I had to retest my program. For some reason though, it doesn't complie anymore?

In my code I'm using SPI.send24 as well as SPI.hasInterruptFlagSet, SPI.clearInterruptFlag and SPI.enableInterrupt. 

I can't find ANYTHING about send24 anywhere, and very little about the others. But I found another SPI project locally, SPI-master, that has the send24 code. It says it is from https://www.pjrc.com/teensy/td_libs_SPI.html, but going there leads nowhere. Not sure what has happened, I feel completely gaslit!

Anyway - I copied the SPI-master into my project to get send24. As for the interrupt stuff, it's not really necessary as it only makes it possible to listen to send completes to trigger Load dac - and this can be done in software without penalty anyway, by adding it to the setting of the last DAC channel.

Ok, so how do we use the DAC8565.

The following pin config works:

pin 1,2, 7 and 8 are the four output channels

pin 3, Vref H, is the high reference voltage. It outputs the internal reference voltage (2.5V) if the internal voltage reference is used, and should be connected to ground through a 150nF cap. If using an external voltage reference instead, it can have an additional 4.8uF (!) cap to ground for reduced noise.

It is important to note that the max output when using the internal reference is 2.5V. To get a 5V output, we need to use an external 5V reference.

It is also important to note that the external reference CANNOT be higher than the Analog voltage AVDD, or the output will be clipped. 

Pin 4, AVdd, power for the analog parts. It may be 3v3 if using the internal 2.5V reference as output, or 5V if using an external reference.

Pin 5, Vref L, the low reference voltage. Usually connected to GND

Pin 6, GND

Pin 9: !Sync. = SPI Chip select

Pin 10: Serial clock

Pin 11: D in, Serial data. Connect to master MOSI

Pin 12, IOVdd. This should match the logic level of the MCU, which for the Teensy is 3v3. However, I had some success setting this to 5V even with 3v3 output, but I get glitches when running the SPI bus at 50MHz. Also, it says in the spec sheet that 3v3 logic has a max bus speed of 25MHz (I have successfully used 50MHz on the current breadboarded circuit, and 46MHz earlier, but IOVdd must be 3v3.

I will try using 5V logic but that requires a high speed level shifter between the Teensy and the DAC.

Pin 13: !RST - when set to 0, all DAC outputs are reset to the value of RSTSEL

Pin 14: RSTSEL - reset select. If 0, DACs power up and reset to 0, if 1 they reset to the middle of the reference voltage.

Pin 15: !Enable - "Connects the SPI interface to serial port". This is currently confusing me though connecting it to 0 works fine.

Pin 16: LDAC: Load Dac. Connect to GND and control this through software or connect to MCU

Running a loop with IOVdd at 3v3, AVdd at 5V and using a 5V external reference

50MHz SPI works fine

There is significant noise on the output

The noise is however only while the SPI bus transfers. This may make it bearable even if present in the real circuit, as we can transfer the data and let the signal settle before turning on the output muxes that load the sample and hold caps.

5V IOVdd also works...

Unfortunately, we get glitches at 5V IOVdd

The glitches go away when reverting to 3v3IOVdd

With MUX

I spent a long time trying to get my 16ch CV buffer to work with the DAC. Turns out I had mislabeled pin D0, it should be next to D1, not next to GND. 

Anyway, once I got that out of the way, the 16ch board works fine:

DAC Output through opamp buffer and 470R to mux. Works great!

Output is very stable. DAC slightly overshoots when switching (meastured after the buffer I think)

I tried various combinations:

5V external reference, 470Ohm resistor directly to DAC

5V external reference, no resistor, DAC directly to mux. DAC has no problem driving the charging

2.5V internal reference, 2x positive gain op amp, 470R input resistor

5V external reference, 470R input, no buffer. Something is very wrong! Not sure exactly what.

Some closeups

Extreme closeup of 2.5V ref through 2x gain and 470R resistor.

Extreme closeup of 5V ref, buffered and 470R resistor. Pretty much the same

Extreme closeup of 5V ref direct from dac without resistor. A tad noisier?

Then some charge times:

Dac output when run as 5V ref direct from DAC without resistor. Rise time is around 5.5uS

5V ref direct from DAC without resistor. Charge time 0 to 5V for CV buffer cap. Around 1.5uS

This is as far as I got, because here I somehow killed the Teensy :-( I would have liked to have the same two checks when running with 2.5V internal reference and 2x gain through 470R. Have to look for a new Teensy

...oh, I found one. Let's go on

Cap charge time through 470R resistor, around 3.4uS

But what if we change to a 220R instead?

Cap charge time through 220R resistor, around 2.2uS

 

That's pretty good. Let's look at the DAC settling time:

Rise time from 0 to 5V, as seen at the output of the buffer after the DAC, is around 2.9uS. The drops in voltage coincides with the charging of the caps and are not present at the DAC output.

All in all, this looks very promising. For my first production version I will use a 2x positive gain buffer with a 220R charging cap.

OB-6 CV generation revisited

After getting the closeups of the OB-6 it's time to put together what I've learned so far.

Hardware

1) The DAC used is AD5668, an 8 channel 16bit DAC with built in voltage reference (2.5 x 2 = 5V). The chip used by Sequential is the AD5668-3 that resets to midscale (2.5V). 

2) The multiplexers are TI CD74HCT4051

3) The op amp buffers are most likely TL06x as that's about the only thing found on the voice card

4) There is no DAC output buffering op amp as that is built into the DAC.

5) I'm not sure what size of sample and hold caps they are using

Timing/performance

Brian from Abstrakt Instruments has a great breakdown of how the refresh is done here:

https://youtu.be/4WwXlRYw_S0?t=1937

Each DAC channel updates 8 cv channels at 24kHz meaning

• DAC channels are updated at 192kHz
• There is about 5.2uS available for refreshing a single CV, this includes time to set the DAC, cap charging and any propagation delays/slew through the mux.
• From the oscilloscope output, a full rail to rail change takes around 3uS

DAC performance

• The DAC has a max SPI speed of 50MHz, meaning one bit takes 20nS to transfer. Each update is 32bits long, meaning updating 8 channels takes at least 32 * 8 * 20nS = 5120nS = 5.12uS.
• Settling time is typically 2.5uS, but can be as bad as 7uS. (But it is stated that this is 1/4 to 3/4 settling so that means that it is only a change of 2.5V?)
• Slew rate is 1.2V/uS

Multiplexer performance

• On resistance is 90-180Ohm (?)
• Propagation delay from in to out is 4nS, higher with higher capacitive load but still in the nS range
• Switch delay is around 20nS
• Charge injection: does not say.

What does this mean in practice: 

Well, we've got 5.2uS to update a single CV. First of all, if updating all channel takes 5.1uS, this cannot be done during that period. We want to update all channels at once, if we didn't we would need separate address lines for all the multiplexers which is infeasible. 

Luckily the DAC has a LDAC pin. This means we can write data to all channels, and when ready, flip the LDAC and load channels at the same time. By writing the next update while the current one charges the capacitors, we have just enough time to do a full 8ch update. We will also have to use hardware "fire and forget" SPI, writing the necessary 32 bytes of data in the background. If we use blocking SPI, we will have no time left between updates to calculate the next bytes!

Next, we still have to let the dac settle before we turn on the multiplexer output, or we would see an error in the voltage. Settle time is, from both the oscilloscope photo and the datasheet, around 3uS, but it could be as bad as 7uS. I would also think that the slew rate of 1.2V/uS also means that it would take around 6uS for a 5V change.

The multiplexer propagation delay is negligible. That leaves 2uS for charging the cap and turning off the mux again. 

Now, as I've noted in earlier posts, I could charge a 10nF cap rail to rail at 40kHz from a TL072, meaning charge times are around 25uS.  2uS means we need to use a cap at least 1/10th that size, or less than 1nF. 

I did some tests with the DAC8830 and a DG408 multiplexer. Using a 1nF cap did NOT let us fully charge the cap rail to rail in the 5.2uS window.  I got close but not close enough. The AD5668 may be able to deliver more current but that remains to be tested. 

So what do I make of all this? 

I suspect that Sequential is "cheating" here. They haven't spec'ed their system for charging rail to rail in <5uS, as they don't have to! The fastest moving signals would be the envelope attacks, and those NEED intermediate steps to sound good (?). 

I have ordered both the AD5668, CD74HCT4051 and TL072. It will be exciting to see the results of using those parts. Will I still have the charge injection issues? Does the AD5668 charge the caps faster? I will definitely post the results!

OB-6 - closeups

I got some incredibly nice closeup pics of the OB-6 voice card (and parts of the mainboard) from a friend of a friend. They make it really easy to figure out what is going on. You can clearly see the thermistor in the VCO expo converter for example, as well as laugh a little about the fact that they use coolaudio chips (Behringer, remember?). 

Pro tip: Use http://www.smdmark.com to figure out what chips are used from their markings!

Here they are:

Coolaudio V2164 quad expo VCAs. Great little chip.

TL064 all the way!

Top left - the green chip with '33' on it is the thermistor, the K4A is a dual 3904 transistor used as an expo converter

DACs, those are AD5668 8 channel 16 bit dacs

Voice card slots. Notice the HCT4051 CV multiplexers in between.